clock skew
英 [klɒk skjuː]
美 [klɑːk skjuː]
网络 时钟偏移; 时钟偏差; 时钟漂移; 时钟脉冲相位差; 时钟偏斜
双语例句
- The error messages you will get from clock skew will not generally be obvious.
在时钟问题中产生的错误消息通常都不太明显。 - Our basic idea is to make use of the permissible clock skew to enhance the timing reliability of a circuit.
我们的基本想法，是利用可允许的时序差异值来提高电路的时序可靠度。 - Concerning the clock skew and clock drift problem in wireless sensor networks, some different methods of synchronization time on synchronization accuracy were studied.
针对无线传感器网络固有的时钟偏移和时钟漂移问题，研究了不同的时间同步方法对同步精度的影响。 - This paper presents an effective approach for clock skew scheduling that can reduce the center error square and assign slacks incrementally.
提出了在时钟偏差规划过程中减小中心误差平方值的增量式松弛量分配方法。 - In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.
在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。 - In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance.
在多FPGA设计中，时钟信号的传输延时造成了FPGA间的大时钟偏差，进而制约系统性能。 - To reduce the runtime for clock skew scheduling, a novel near-linear time approach is proposed.
为了减少时钟偏差规划所需的时间，提出一种准线性时间复杂度的时钟偏差规划方法。 - Clock skew is in a synchronization digital integrated circuit design difficult problem.
时钟偏移是同步数字集成电路设计中的一个难题。 - To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured.
为了克服制程、电压、温度变异所造成的影响，自动时脉偏移同步方案可以在晶片制造出来之后动态地调整并降低时脉偏移。 - Mechanism about the clock skew of synchronism sequential circuit has been presented, based on analyzing the characteristics of programmable resources and sequential circuit in FPGA.
在分析星载FPGA内时序电路特性以及FPGA可编程资源特性的基础上，指出了FPGA内同步时序电路出现时钟偏斜现象的机理。 - In this thesis, we show that how FFs are connected by PDs can also greatly influence the final clock skew due to limitations of a practical ADB and PD design.
在这篇论文中，我们提出由于实际的可调变延迟缓冲器及相差侦测器设计上有其物理上的限制，相差侦测器连接正反器的拓墣也会影响最后的时脉偏移。 - We first analyze the worst-case clock skew of PD connection structures.
在这篇论文中，我们首先分析给定相差侦测器架构下最糟的时脉偏移量。 - Analysis of the Clock Skew in ASIC Design
专用集成电路设计中的时钟偏移分析 - Then we propose an algorithm to generate an optimal PD connection structures resulting in the minimum clock skew.
接著，我们提出一个能够产生最小时脉偏移之相差侦测器架构的演算法。 - The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。 - Asynchronous design methodology has become one of the most promising directions in SOC design because asynchronous circuit possesses the advantages of low power, low noise, no clock skew, high robust and modularization.
异步电路在低功耗、低噪声、抗干扰、无时钟偏移和模块化设计等方面有较高的性能。在SOC芯片设计中，异步设计技术逐渐成为研究的热点。 - Estimation of Clock Skew in Delay Measurement
时延测量中估算时钟时滞的方法 - The buffer insertion is hierarchically arranged, as to reduce the sensitivity of clock skew.
算法中的BUFFER定位是层次式的，有利于减少时钟偏差敏感度。 - A New Approach for Removing Clock Skew and Resets from One-Way Delay Measurement
一个消除单向时延测量中时钟频差和时钟重置的新方法 - In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。 - DCM can synthesize the clock frequency, phase shift and eliminate clock skew, solving many clocking issues.
DCM具有频率综合、相移功能，能够消除时钟偏移，解决很多系统中的时钟问题。 - Analysis of Clock Skew in ASIC Design
ASIC设计中时钟偏移分析 - Serial communications based on SERDES adopt the clock_data recovery ( CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。 - The clock period minimization and timing failure probability minimization are two conflicting targets in clock skew scheduling.
时钟周期最小化和时序失效概率最小化是时钟偏斜规划中两个冲突的目标。 - With the deep analysis of the system-level timing synchronization problem of embedded memory, this thesis proposes a useful clock skew scheduling based on the particle swarm optimization ( PSO) algorithm.
本文深入分析了嵌入式存储器在系统级的同步时序问题，提出了一种基于粒子群优化（PSO）算法的有用时钟偏差规划方法。 - After introduction of the working principle of synchronous sequential circuits, as well as clock skew and jitter definition, and clock tree definition, structure and comparison of three ways of CTS, it mentions the importance of timing constraints files.
在时钟树综合部分，主要介绍同步时序电路工作原理，以及时钟偏差和时钟抖动的定义，时钟树的定义、结构和综合方式的比较，最后提到时序约束文件的重要性。 - The paper investigated optimized design of the circuit clock tree to reduce clock skew which affect the circuit function.
论文对时钟树设计进行了优化，减少了时钟偏差的对电路功能的影响。 - Sampling can not be achieved at optimal time instant because of the channel propagation delay and the clock skew between sending and receiving, so there exists large difference between the collected data and real data.
由于信道传输延时以及收发两地时钟偏差，将使采样无法在最佳时刻进行，这样采集到的数据与真实数据之间会存在较大误差。 - Reduce clock skew and clock delay is the significant target of clock network plan and clock routing.
减小时钟偏差和时钟延迟是时钟网络规划及时钟布线的主要目标。